IEEE

Low power Viterbi decoder design based on reversible logic gates

Abstract: In recent trends of VLSI technology the reversible logic has became the major area of research in optimization of area, power and speed constraints. The reversible logic has equal number of ...
Tom's Hardware

Migliori decoder digitale terrestre DVB-T2 (luglio 2026)

Il passaggio al digitale terrestre di seconda generazione non è più soltanto una prospettiva futura: una parte dell'offerta Rai è già trasmessa in DVB-T2 e il calendario di adozione continua a ...
IEEE

Power efficient low latency survivor memory architecture for Viterbi decoder

Abstract: Viterbi decoder is a common module in communication system in which power and decoding latency are constraint. Register exchange (RE) architecture has the lowest decoding latency L. However, ...
GitHub

(2,1,6) Convolutional Code — Encoder + Viterbi Decoder

A from-scratch C implementation of a rate-1/2, constraint-length K = 7 convolutional code with a 64-state, soft- and hard-decision Viterbi decoder, plus a BER-vs-SNR Monte-Carlo simulation over a BPSK ...
GitHub

dmr_34_viterbi.c

static const uint8_t s_constellation_map[16] = {11, 12, 0, 7, 14, 9, 5, 2, 10, 13, 1, 6, 15, 8, 4, 3}; // FSM mapping: for prev_state in [0..7], and tribit t in [0..7 ...