IEEE

YAXY: A New Hybrid FPGA-Based Hardware Acceleration of TFHE

Abstract: Fully Homomorphic Encryption (FHE) enables direct computation on ciphertexts, thereby ensuring data privacy during processing. However, its widespread application is impeded by high ...
GitHub

FPGA-Based Drone Detection and Classification System Using YOLOv8n on ZCU104

Real-time FPGA-accelerated drone detection system using YOLOv8n, AMD Xilinx ZCU104, DPUCZDX8G, and a custom Vivado HLS-based NMS accelerator. This project implements a real-time FPGA-based drone ...
Electronic Design

AMD Moves from HBM to LPDDR5X with New Memory-on-Package SoC

The company is replacing hard-to-find high bandwidth memory (HBM) with LPDDR5X in its latest Versal processor.
IEEE

DAHBM-GCN: A Flexible Graph Convolution Network Accelerator With Multiple Dataflows and HBM

Abstract: Graph-structured data has been widely applied in transportation, molecular, and e-commerce networks, etc. Graph Convolutional Network (GCN) has emerged as an efficient approach to processing ...
Semiconductor Engineering

From Host Node To Heterogeneous Rack: Rethinking The AI CPU

As AI infrastructure fragments into specialized tiers, CPUs are becoming the orchestration layer for agentic workloads.
Hackaday

Porting The Nvidia GPU Driver To Haiku For 3D Acceleration

As good as a desktop OS may be, at some point it has to feature accelerated 3D graphics. This has been a bit of a sticking ...
note

New Place

Actual cutting-edge CPUs and ASICs are not made by a single genius, but by a team of hundreds to thousands of people, including architects, RTL designers, physical designers, verification engineers, ...