EDN

SoC test requirements debated

BALTIMORE — The prevalence and escalating cost of system-on-chip (SoC) designs are forcing a reexamination of existing approaches to design and test, according to EDA and test industry executives at a ...
EDN

Indian researchers propose new SoC test method

BANGALORE, India — With efficient test access architecture of much interest to the SoC design and test community, two researchers at an Indian technical institute have proposed a design-for-test ...
Semiconductor Engineering

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC

A new technical paper titled “Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip” was published by researchers at Inha University and Teradyne. ...
Yahoo Finance

Advantest Unveils T2000 AiR2X Air-Cooled SoC and Power Analog Test Solution

T2000 AiR2X air-cooled SoC and power analog test solution · GlobeNewswire Inc. TOKYO, Dec. 11, 2025 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) ...
Electronic Design

Tackling Next-Generation RF SOC Test

Developing an automated production test solution for current and next-generation complex RF SIP/SOC devices is an increasingly difficult task. Both the test program and the device interface board (DIB ...
Nasdaq

Advantest Introduces Evolutionary V93000 EXA Scale™ SoC Test System

TOKYO, Sept. 23, 2020 (GLOBE NEWSWIRE) -- Leading semiconductor test equipment supplier Advantest Corporation (TSE: 6857) has announced its next-generation V93000 testers targeted at advanced digital ...