Semiconductor Engineering

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling

The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, ...
Semiconductor Engineering

Have It All With No-Compromise DFT

The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels ...
Electronic Design

What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...
Electronic Design

Synthesis of Design Rules and Patterns

This file type includes high-resolution graphics and schematics when applicable. Michael White, Director of Product Marketing, Calibre Physical Verification products, Mentor Graphics In recent years, ...
EDN

Methodology automates mixed-signal IP retargeting

Flexibility and automation. Those two terms can determine a company's profitability in today's competitive marketplace. Chip developers are faced with more complex designs, shrinking design windows ...