Electronic Design

Formal Methodology Validates Cache-Coherence Protocol

Moreover, cache coherence is an especially important protocol to verify. A cache-coherence bug could result in a silent data corruption that would disrupt system functionality. A formal tool for ...
Semiconductor Engineering

Heterogeneous Cache Coherence Requires A Common Internal Protocol

Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and ...
Design-Reuse

Using OCP and Coherence Extensions to Support System-Level Cache Coherence

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
Design-Reuse

Co-Designed Cache Coherency Architecture for Embedded Multicore Systems

One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...
Electronic Design

Adding Cache to IPs and SoCs

Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. Technologies like AMBA protocols facilitate cache coherence and efficient data management across CPU ...
Semiconductor Engineering

The High But Often Unnecessary Cost Of Coherence

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized ...