EDN

Design for testability: separating the myths from reality

The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT). This will take the form of a “test re-use” strategy ...
Semiconductor Engineering

Testability Analysis Based On Ever-Evolving Technology

The complexity of system-on-chip (SoC) designs continues to grow, so the corresponding design-for-test (DFT) logic required for manufacturing has become more advanced. Design teams are challenged by ...
EDN

Design for testability—a boundary-scan primer

Failures have been present in electronic products since the days of vacuum tubes, and despite enormous development and production improvements, no manufacturing technique can guarantee a 100% ...
Semiconductor Engineering

A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)

A technical paper titled “Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation” was published by researchers at University of Florida. “Scan-based ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Design-Reuse

Meridian DFT Multimode Design for Testability Sign-Off

Meridian DFT (Design For Test) from Real Intent delivers multimode design-for-test (DFT) static sign-off to ensure maximum scan coverage and silicon s ...