Electronic Design

Signoff Evolves From Design-Rule Checking To Yield Analysis

IC designers are a lucky bunch. Through many years of semiconductor process evolution, the impact of manufacturing limitations and variations on layout could be encapsulated in relatively simple ...
EDN

New error comparison scheme proposed for design rule checking flows

BENGALURU, India — With design rule checking becoming hugely complex in the deep sub-micron regime, there is a large run time for physical verification tools, for the number of design rules that must ...
Business Wire

Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite

WILSONVILLE, Ore.--(BUSINESS WIRE)--Mentor Graphics Corporation (NASDAQ:MENT) today announced the release of a major new product in the HyperLynx® suite, the market-leading, high-speed analysis ...
Electronic Design

Design-Rule Checker Sports Foundry Compatibility

Advances in design checking capability, including foundry-compatible design-rule checking (DRC) and background DRC, are among the features of HiPer Verify, the first tool in a line of IC layout and ...
Semiconductor Engineering

Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking

Early-stage layout vs. schematic (LVS) and circuit verification typically return large numbers of connectivity errors, which can be a critical bottleneck for both LVS and physical verification flows ...
Semiconductor Engineering

Earlier SoC Design Exploration And Verification Gets Better Designs To Tapeout Faster

Between the complexity of advanced node design verification and the competition to be first to the market, system-on-chip (SoC) designers no longer have the luxury of waiting until each sub-block of a ...
EDN

A primer on logical equivalence checking (LEC) using Conformal

Designing a chip is a complex process. It starts with defining the architectural requirements, then microarchitecture development, followed by RTL design and functional verification. Then the design ...