Electronic Design

DFT Propels SoC IC Testing

The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

DFT Analyzer Validates Design-For-Test Features

Asset InterTech has announced its DFT Analyzer, which according to the company reduces manufacturing and test costs by validating the boundary-scan design-for-test features in a circuit-board design ...
EDN

Is DFT ready for prime time?

Over the last few years, design-for-test (DFT) chip-testing techniques such as internal scan (ISCAN), automatic test-pattern generation (ATPG), built-in self-test (BIST), and boundary scan (BSCAN) ...
Semiconductor Engineering

Hierarchical DFT: Proven Divide-And-Conquer Solution Accelerates DFT Implementation And Reduces Test Costs

Implementation of the most challenging DFT tasks is greatly simplified by the proven and widely-adopted automation available in Tessent products. This whitepaper describes the basic components of an ...
Semiconductor Engineering

An Optimal Path To DFT Automation

To keep up with time-to-market demands when SoCs keep increasing in size and complexity requires the adoption of better DFT flows and technologies. One of the most successful changes in ...
FOX31 Denver

Siemens automates 2.5D and 3D IC design-for-test with new Tessent Multi-die solution

Global leader in design-for-test (DFT) technology paves the way for mainstream adoption of 3D ICs Innovative solution dramatically streamlines DFT cycles for highly complex multi-die designs PLANO, ...